Run design-rule checks

You want to validate a PCB before sending it to fab. This guide runs the core design-rule check plus the signal-integrity checks, shows you how to read and act on the results, and then re-runs to confirm a clean board. It assumes an MCP-connected agent (see the quickstart).

1. Run the core DRC

Start with the full design-rule check. It covers clearances, trace widths, annular rings, and connectivity against the active net classes.

“Run run_drc on the current board and list every violation with its location and rule.”

Read the report by category before touching anything. A handful of clearance violations clustered in one area usually means one trace or one part is misplaced — fix the cause, not each symptom.

2. Check controlled impedance

For any net with a target impedance, verify the trace geometry produces it. Check both the nominal value and the value at your operating frequency, since dispersion shifts impedance on fast edges.

“Call check_impedance on the impedance-controlled nets, then check_impedance_at_frequency at the bus’s operating frequency.”

An impedance miss almost always traces back to trace width or the layer stackup, not routing.

3. Check differential pairs

Validate differential-pair geometry — spacing, coupling, and length matching.

“Run check_diff_pair on the USB and Ethernet pairs.”

Failures here mean fixing intra-pair spacing or length skew.

4. Check BGA escape feasibility

For any BGA, confirm the fanout can actually escape the package given your layer count and via rules. Catching an infeasible escape now is far cheaper than discovering it mid-route.

“Call check_bga_escape_feasibility for the main BGA and tell me if the current layer count is enough.”

If it reports infeasible, the fix is usually adding a layer or switching to a smaller via style.

5. Render for a visual check

Render the board so you can see the reported issues in context rather than as coordinates.

“Render the board with render_pcb_svg so I can see the flagged areas.”

6. Iterate and re-run

Work through the findings, then re-check. A quick map from finding to fix:

• Clearance / width (run_drc) — move traces or adjust the net class.
• Impedance (check_impedance, check_impedance_at_frequency) — adjust trace width or stackup.
• Diff pair (check_diff_pair) — fix spacing or length matching.
• BGA escape (check_bga_escape_feasibility) — add a layer or change via style.

After each round of fixes, re-run run_drc and the relevant signal-integrity check, then render_pcb_svg again to confirm visually. Repeat until the board reports clean. Once it does, move on to Export for fabrication.